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JTAG Technologies BSDL generation/verification system combines advanced software with a unique hardware interface and automatically verifies an existing BSDL (Boundary-Scan Description Language) file or creates a BSDL file for the device if none exists from a known good sample device. The system complies with the recognized standard for BSDL descriptions – IEEE Std. 1149.1b . BSDL files describe the boundary-scan characteristics of a specific device in terms of scan register lengths, ID codes, instruction codes, etc.. and are a fundamental input to ATPG (e.g. ProVision) and other boundary-scan software tools.

    • Supports up to 512 signal pins
    • Easy-to-use software and hardware
    • Creates a BSDL model from hardware
    • Includes a JT 3707 controller


  • Create and verify Boundary-Scan Description Language (BSDL) files using the actual integrated circuit
  • Wizard guides the user through the generation / verification process
  • Graphical editor provides interactive preparation of pin list for PGA and BGA device packages (in case no BSDL file exists)
  • Table-structured editor generates pin list definition interactively for other device package types (in case no BSDL file exists)
  • Extensive reporting features: cell list, pin list, input list, output list, register information
  • Support for wide range of package types: PGA, BGA, QFP, TSOP, etc. with automatic wiring/netlist generation software
  • 512 I/O channels each with independent sense, drive, bi-directional, and tri-state capabilities
  • 1, 2, 4, or 8 I/Os selectable per segment of 16 I/Os
  • Input and output voltage levels separately programmable per segment and segments can be individually bypassed
  • Programmable input threshold from 0 V to 4.1 V in steps of 0.1 V
  • Programmable output voltage from 1.5 V to 3.6 V in steps of 0.1 V
  • Internal 5 V power supply plus three flexible power supply points
  • High-speed TCK (up to 40 MHz) for maximum performance
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